A successive approximation type AD converter typically serves to convert an analog input signal into a binary digital value by a binary search method. The successive approximation type AD converter is classified roughly into a synchronous type and an asynchronous type.
In the synchronous AD converter, a sampling clock used for determining a sampling period are generated based on the externally supplied clock and a timing clock used for controlling the operation of a comparator. The AD converter operates in synchronization with these clocks. Since the synchronous AD converter requires a circuit for generating these clocks and also requires wiring lines for clocks to extend therein, the consumption current becomes relatively large and the circuit is increased in area.
The asynchronous AD converter serves to start the comparison operation in the next cycle based on the signal showing that a comparison operation has been completed, and thus, does not require supply of a clock signal in a constant cycle. Accordingly, the power consumption and the area can be reduced as compared with the case of the synchronous AD converter (for example, see “A 6-bit 600-MS/s 5.3-mW Asynchronous ADC in 0.13-μm CMOS” by Chen, et. al., IEEE Journal of Solid-State Circuits, Vol. 41, December in 2006, pages 2669 to 2680 (Non-Patent Document 1)).
According to the asynchronous-type AD converter, however, as the absolute value of the potential difference between the input analog signal and the reference signal becomes smaller, the time until the output signal of the comparator settles becomes longer. In the case where the absolute value of the potential difference between both signals is extremely small, the required number of comparison for one AD conversion cannot be carried out to the end, thereby leading to an extremely large AD conversion error.
Japanese Patent Laying-Open No. 2010-45579 (PTD 1) discloses a comparison circuit configured to shorten a determination time period. Specifically, when comparing an input signal and a reference signal, the comparison circuit in this document generates the first comparison value larger than the reference signal by a predetermined value and the second comparison value smaller than the reference signal by the predetermined value. The comparison circuit includes: the first comparator generating the first determination signal in accordance with the result obtained by comparing the input signal and the first comparison value; and the second comparator generating the second determination signal in accordance with the result obtained by comparing the input signal and the second comparison value. The comparison circuit further includes an output selection circuit: detecting one of the first determination signal and the second determination signal that is first generated; and selecting the first generated signal to output the selected signal as a determination signal.